In semiconductor devices, it is well known to have thin film resistors embedded in the back-end-of-the-line (BEOL) of the chip through either a damascene process or a subtractive etch method. BEOL thin film resistors are preferred over other types of resistors because of lower parasitics. However, the sheet resistivity of the various resistors formed over the entire wafer may vary and go beyond specifications due to poor process control. In an advanced manufacturing line, wafers out of specification are often scrapped for quality control.
The resistor is one of the most common electrical components used in almost every electrical device. Conventionally, doped polysilicon is used as the material of a resistor. However, the conventional resistor can only provide a limited resistance within a limited dimension as manufactures keep shrinking the device feature size down. To overcome this problem, new materials with higher resistivity and new integrations are required for fabrication of thin film resistors in a highly integrated semiconductor device.
Resistive thin films such as CrSi and TaN are often used as resistors in semiconductor devices. Integration schemes used to fabricate the resistor components within the interconnect structure fall into two primarily categories. In the first integration scheme, a thin film resistor is formed, by etching on top of an insulator. A metallic layer is deposited on top of the resistive layer and is used to protect the resistor layer from being damaged during the sequential etching process. After the resistor has been defined, the underlying dielectric layer is then patterned and etched to define the interconnect pattern. Finally, a metallic layer for the interconnect is deposited, patterned and etched. Although the protective layer is capable of protecting the resistive layer, the provided protection is limited and the resistive layer may still be damaged during the etching process. This integration scheme is disclosed, for example, in U.S. Pat. No. 6,207,560.
In the second integration scheme, a thin film resistor is formed, by etching on top of an insulator. An interlevel dielectric is then deposited, followed by patterning and etching processes to define an upper level interconnect structure with vias connected to the underlying thin film resistor. A planarization process is usually required after deposition of the interlevel dielectric material in order to compromise any possible topography related issues caused by the underlying resistors.
Some additional prior art disclosures of BEOL resistors and methods of fabricating the same include, for example: U.S. Patent Application Publication No. 2004/0027234, U.S. Pat. No. 6,232,042, U.S. Pat. No. 6,207,560, U.S. Pat. No. 6,083,785, and U.S. Pat. No. 5,485,138.
Resistors can be trimmed by using laser or high-energy particle beams in order to set the resistance of the resistor. The prior art trimming processes are not clean and therefore have never become a common practice. Resistors can also be programmed by using a shut resistor to deselect at least a portion of the resistor from a chain of resistors within a circuit. This prior art method has two problems; first the resolution of the programming is limited by the least significant bit device size. Secondly, the shut device itself has some resistance. The tuning precision is thus poor.
In view of the above, there is a need to provide a BEOL resistor that can be electrically programmed without the need of using prior art shut resistors and wherein the resistance of the resistor can be set without the need of using prior art trimming methods.